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DEVICE SPECIFICATION E4/STM-1/OC-3
ATM TRANSCEIVER
S3031B S3031B GENERAL DESCRIPTION
The S3031B transceiver chip is a fully integrated CMI encoding transmitter and CMI decoding receiver. The chip derives high speed timing and data signals for SONET/SDH or PDH-based equipment. The circuit is implemented using AMCC's proven Phase Locked Loop (PLL) technology. Figures 1a and 1b show typical network applications. The S3031B has two independent VCOs which are synchronized to the local NRZ transmitted data and the received CMI data respectively. The chip can be used with either a 19.44 MHz or a 38.88 MHz reference clock when operated in the SONET/SDH OC-3 mode. In E4 mode the chip can be operated with a 17.408 MHz or a 34.816 MHz reference in support of existing system clocking schemes. On-chip coded-mark-inversion (CMI) encoding and decoding is provided for 139.264 Mbps and 155.52 Mbps interfaces. The low jitter PECL interface for the serial data inputs and the PECL nibble clock interface guarantee compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3031B is packaged in a 0.65 mm pitch 100-pin PQFP/TEP. The S3031B provides the major active components onchip for a coaxial cable interface, including analog transformer driver circuitry and equalization interface circuitry. Discrete controls permit separate selection of CMI or NRZ operation and analog (coaxial copper) or PECL (optical module) media interfaces. Both line loopback and diagnostic local loopback operation are supported.
E4/STM-1/OC-3 ATM TRANSCEIVER FEATURES
* * * * * * * * * * * * * Complies with Bellcore and ITU-T specifications On-chip high-frequency PLLs for clock generation and clock recovery On-chip analog circuitry for transformer driver and equalization Supports 139.264 Mbps (E4) and 155.52 Mbps (OC-3) transmission rates Supports 139.264 Mbps and 155.52 Mbps Coded Mark Inversion (CMI) interfaces TTL Reference frequencies of 19.44 and 38.88 MHz (OC-3) or 17.408 and 34.816 MHz (E4) Interface to both PECL and TTL logic Lock detect on clock recovery function -- monitors run length and frequency Serial and 4 bit (nibble) system interfaces Low jitter PECL interface +5V operation 100 PQFP/TEP package Supports both electrical and optical interfaces
APPLICATIONS
* * * * * * * * * ATM over SONET/SDH OC-3/STM-1 or E4-based transmission systems OC-3/STM-1 or E4 modules OC-3/STM-1 or E4 test equipment Section repeaters Add Drop Multiplexers (ADM) Broadband cross-connects Fiber optic terminators Fiber optic test equipment
Figure 1a. Electrical Interface
E4/STM-1/OC-3 OVERHEAD PROCESSOR
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps CMI
COAX
XFMR S3031B XCVR
139.264/155.52 Mbps CMI
139.264/155.52 Mbps NRZ
XFMR
COAX
OSC
17.408/19.44 MHz
Figure 1b. Optical Interface
139.264/155.52 Mbps NRZ 139.264/155.52 Mbps OTX
E4/STM-1/OC-3 OVERHEAD PROCESSOR
139.264/155.52 Mbps NRZ
S3031B XCVR
139.264/155.52 Mbps ORX
OSC
17.408/19.44 MHz
August 19, 1999 / Revision D
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S3031B SONET/SDH OVERVIEW
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, form a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: * Photonic * Section * Line * Path Figure 2 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to optical and back with no overhead. It is responsible for
E4/STM-1/OC-3 ATM TRANSCEIVER
transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates. Data Rates and Signal Hierarchy Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS-N signal is made up of N byte-interleaved STS-1 signals. The optical counterpart of each STS-N signal is an optical carrier level-N signal (OC-N). The S3031B supports OC-3 rates (155.52 Mbps). Frame and Byte Boundary Detection
Table 1. SONET Signal Hierarchy
Elec.
STS-1 STS-3 STS-12 STS-24 STS-48
ITU-T
STM-1 STM-4 STM-16
Optical Data Rate (Mbps)
OC-1 OC-3 OC-12 OC-24 OC-48 51.84 155.52 622.08 1244.16 2488.32
The SONET/SDH fundamental frame format for STS-3 consists of nine transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes. This pattern of 9 overhead and 261 SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 3.) For more details on SONET operations, refer to the Bellcore SONET standard document.
Figure 2. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Figure 3. STS-3/OC Frame Format
Layer Overhead (Embedded Ops Channel)
A1 B1 D1 H1 A1 * * H1 B2 * * * Z1 A1 * * H1 B2 * * * Z1 A2 E1 D2 H2 K1 D5 D8 D11 Z2 A2 * * H2 * * * * Z2 A2 * * H2 * * * * M1 J0 F1 D3 H3 K2 D6 D9 D12 E2 Z0 * * H3 * * * * * Z0 * * H3 * * * * *
Path layer Line layer Section layer
Path layer Line layer Section layer
576 Kbps
9 Rows
9 x 261 = 2349 bytes
B2 D4
192 Kbps
D7 D10
Photonic layer
Photonic layer 0 bps
S1
Transport Overhead
Fiber Cable End Equipment
Synchronous Payload Envelope 261 Columns
End Equipment
9 Columns
v
125 sec
v
2
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER S3031B OVERVIEW
The S3031B transceiver can be used to implement the front end of STS-3, OC-3 or E4 equipment. The block diagram in Figure 9 shows the basic operation of the chip. When the S3031B is operating in the nibble parallel mode, the transmitter VCO is synchronized to the 38.88 MHz nibble clock as both the reference clock and the data transfer clock. If the serial input is selected as the transmitter data source the VCO will be synchronized directly to the incoming data. Serial operation of the S3031B transmitter section is possible with either the 38.88 MHz or 19.44 MHz reference oscillator. In the absence of incoming serial data the transmitter section will operate as a clock synthesizer. The receiver section performs clock recovery by synchronizing its on-chip VCO directly to the incoming data stream. In E4 operation, the 34.816 MHz REFCLK is used as the nibble clock. Thus in Nibble parallel mode, the S3031B transmitter section supports unscrambled E4 operation. If serial mode is selected, the NRZ E4 data must be scrambled to allow the PLL to lock onto the data transitions. The S3031B provides a PECL output for an optical interface and two transformer driver outputs for an electrical interface. One of these drivers is a monitor output. The S3031B provides a PECL input for an optical interface and an analog input for an electrical interface. The transformer driver outputs are separately enabled. Status outputs detect the disabled, stuck at 1, stuck at 0, and non-CMI states to qualify the transformer driver outputs. The CMI outputs, analog equalizer input section, and PLL sections are independently powered for isolation and for power savings when the device is used in single function applications.
S3031B S3031B TRANSMITTER ARCHITECTURE/FUNCTIONAL DESIGN
Transmitter Operation The S3031B chip's transmitter section performs the last stages of digital processing of a transmit SONET STS-3 or ITU-T E4 serial or 4-bit nibble parallel data stream. Clock Recovery If the serial input data has been selected, and serial data is present at the TSDATIP/N inputs, the clock is recovered from the serial data stream at 139.264 MHz or 155.52 MHz and synthesized to 278.528 MHz or 311.04 MHz to CMI encode the incoming data. In clock recovery mode, the transmitter PLL continues to monitor the reference clock with respect to the VCO and the activity of the serial data input. The transmitter PLL will re-lock to the reference clock under the following conditions: 1. If the serial data inputs contains insufficient transition density (run length greater than 100 to 200 bit times). 2. If the VCO drifts away from the local reference clock by more than 1000 ppm. If either XFRMENA or XFRMENB are enabled (logic Low) the density or frequency error defined above will set the appropriate status (XFRMSTATA and/or XFRMSTATB) to the low or fault state. The selected drive status bits will return to the High or clear state and the PLL will again lock to the data if the serial data contains sufficient transition density (less than 100 to 200 bit times between rising edges), and the serial clock is within 250 ppm of the reference clock determined frequency. Optical and Electrical Interfaces The digital data outputs (TSDATOP/N) are the PECL outputs for an optical interface and are to be connected to an electrical to optical converter, as shown in Figure 17. This data is also routed to two on-chip transformer drivers and sent out on XFRMDRVA and XFRMDRVB to drive the transformers of the electrical interface, as shown in Figure 19. These outputs are shut off when the reset is active, XFRMEN is active, or when the chip is in NRZ mode and the data inputs are in the logic zero state. The electrical characteristics for the transformer drivers are shown in Table 9.
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S3031B
Parallel-to-Serial Converter The parallel-to-serial converter shown in Figure 9 is comprised of two 4-bit registers. The first register latches the data from the PIN[3:0] bus on the rising edge of REFCLK. The second register is a parallel loadable shift register which takes its parallel input from the first register. The parallel data transfer between registers is accomplished on the falling edge of REFCLK. The serial data is shifted out at the serial bit rate to the CMI encoder. CMI Encoding Coded Mark Inversion format (CMI) ensures at least one data transition per 1.5 bit periods, thus aiding the clock recovery process. Zeros are represented by a Low state for one half a bit period, followed by a High state for the rest of that bit period. Ones are represented by a steady Low or High state for a full bit period. The state of the ones bit period alternates at each occurrence of a one. Figure 4 shows an example of CMI-encoded data. The STS-3 electrical interface and the E4 interface are specified to have CMI-encoded data. The CMI encoder on the S3031B accepts serial data from TSDATIP/N at 139.264 or 155.52 Mb/s. The data is then encoded into CMI format, and the result is shifted out with transitions at twice the basic data rate. The CMISEL input controls whether the CMI encoder is in the data path. A CMI code violation can be inserted for diagnostic purposes by activating the DLCV input. The DLCV input is sampled on every cycle of the serial clock to allow the single or multiple line code violations to be inserted. This violation is either an inverted zero code or an inversion of the alternating ones logic level, depending on the state of the data. Subsequent one codes take into account the induced violation to avoid error multiplication. Jitter Generation Jitter Generation is defined as the amount of jitter at the OC-3 or E-4 output of equipment. Jitter generation for OC-3 shall not exceed 0.01 UI rms when measured using a highpass filter with a 12 kHz cutoff frequency. For STM-1 and E4, the jitter generated shall not exceed the specifications shown in Figure 5. In order to meet the SONET, STM-1 E4 jitter specifications as shown in Figure 5, the TSDATIP/N serial data input must meet the jitter characteristics as shown in Figure 6.
E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 4. CMI Encoded Data
0 0 1 0 1 1 1 0
A2
A1 t
Figure 5. Jitter Generation Specifications Compliant to G.823 and G.825
A1
A2 f1 f2 A1 0.01 1.5
(1) (2)
f3 A2 0.01(1) 0.15(2)
f1(Hz) f2(kHz) f3(MHz) OC-3 STM-1 E4
1. UI rms 2. UI p-p
-- 500 200
-- 65 10
-- 1.3 3.5
(2) 1.5(2) 0.075
Figure 6. S3031B Maximum Allowable Input Jitter
A1 Slope = +20 dB/decade
A2 500Hz f2 f2(kHz) OC-3 STM-1 E4
1. UI rms 2. UI p-p
225 kHz 1.3 MHz A1 A2
-- 65 10
0.005(1) 0.005(1) 1.45(2) 0.10(2) 1.45(2) 0.025(2)
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E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 7. Mask of a pulse corresponding to a binary 0 Compliant to G.703
S3031B
T=
7.18 ns for E4 6.43 ns for 155 CMI
Figure 8. Mask of a pulse corresponding to a binary 1 Compliant to G.703
t=
1.35 ns for E4 1.20 ns for 155 CMI
T=
7.18 ns for E4 6.43 ns for 155 CMI
Notes: 1. The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the dotted area, bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. The possibility of relaxing the amount by which the overshoot may exceed the steady state level is under study. 2. For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2 ns. 3. The inverse pulse in Figure 8 will have the same characteristics, noting that the timing tolerances at the zero level of the negative and positive transitions are 0.1 ns and 0.5 ns respectively.
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S3031B
Figure 9. S3031B OC-3/STM-1/E4 Transceiver
CAP1 CAP2 LOOP FILTER TX VCO
E4/STM-1/OC-3 ATM TRANSCEIVER
REFCLK TSTCLKEN REFSEL CMISEL TXRSTB DLCV CLOCK DIVIDER C M I 2
TREFCLKOUT
TSCLKOP/N XFRMSTATA/B TRANSFORMER DRIVERS XFRMDRVA
4 PIN[3:0]
4:1 PARALLEL TO SERIAL
LLEB (LINELOOP)* TX PHASE DETECTOR 2:1 MUX (LOOPDATA)*
XFRMDRVB
TSDATOP/N
TSDATIP/N XFRMENA/B SERDATEN CAP3 CAP4 SERDSEL 2
2:1 MUX
LOOP FILTER
RX VCO
POCLK TSTCLKEN TESTCLK CMISEL RXRSTB GIN GOUT G CLOCK DIVIDER C M I LOCK DETECTOR
RSCLKOP/N LCV
LOSOUT
BUFINA, BUFINB BUFOUT LOSOPT LOSIN LOSREF RSDATIP/N
2
RX PHASE DETECTOR 2:1 MUX (LINELOOP)* 2:1 (LOOPDATA)* MUX DLEB 2:1 MUX 1:4 SERIAL TO PARALLEL
RSDATOP/N
4 POUT[3:0]
ANDATIN EQUALSEL
* Internal Connections Only
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E4/STM-1/OC-3 ATM TRANSCEIVER S3031B RECEIVER OPERATION
The S3031B transceiver chip provides the first stage of the digital process of a receive SONET STS-3 or ITUT E4 serial bit stream. A Coded Mark Inversion (CMI) decoder can be enabled for decoding STS-3 electrical and E4 signal. The recovered and decoded signal is output as both retimed bit-serial 155.52 or 139.264 Mbps NRZ data and as a 38.88 or 34.816 Mbyte/s 4-bit nibble parallel outputs. Clock recovery is performed on the incoming scrambled NRZ or CMI-coded data stream. A reference clock is required for phase locked loop start-up and proper operation under loss of signal conditions. An integral prescaler and phase locked loop circuit is used to multiply this reference frequency to the nominal bit rate. Clock Recovery The clock recovery function, as shown in the block diagram in Figure 9, generates a clock that is frequency matched to the incoming data baud rate at the RSDATIP/N differential inputs. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. Output pulses from the discriminator indicate the required direction of phase corrections. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) to which the PLL locks when data is lost. When the Test Clock Enable (TSTCLKEN) input is set high, the clock recovery block is disabled. The Test Clock (TESTCLK) is used as the bit rate clock input in place of the recovered clock. This feature is used for functional testing of the device. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET or E4 data signal. This transfer function yields a typical capture time of 16 s for random incoming NRZ data. The total loop dynamics of the clock recovery PLL yield a jitter tolerance which exceeds the minimum tolerance proposed for OC-3/STM-1/E4 equipment by the Bellcore and ITU-T documents, shown in Figure 12. Loss of Signal Optical and Electrical Interfaces
S3031B
The digital data inputs (RSDATIP/N) are the PECL inputs from an optical to electrical converter, as shown in Figure 16. The data input for the coaxial interface is ANDATIN, which is the serial data input from the equalizer circuit and should be connected as shown in Figure 19. The EQUALSEL input is used to select either RSDATIP/N or ANDATIN. CMI Decoding The CMI decoder block on the S3031B accepts serial data from the TSDATIP/N input at the rate of 139.264 or 155.52 Mbps. The incoming CMI data, which has transitions that represent this data rate (the clock associated with this data would be running at twice this rate), is then decoded from CMI to NRZ format.
The clock recovery circuit monitors the incoming data stream for loss of signal. If the incoming encoded data stream has had no transitions continuously for 100 to 200 recovered clock cycles, loss of signal is declared and the PLL will switch from locking onto the incoming data to locking onto the reference clock per the requirements of G.775. Alternatively, the loss-of signal (LOSIN) input can force a loss-of-signal condition. This signal is compared internally against the LOSREF input reference voltage. This input can be set to meet the conditions shown in Figure 10. If the zero to peak signal level drops below the LOSREF/20 voltage level for more than 100 to 200 bit intervals, a loss of signal condition will be indicated on the LOSOUT pin and the PLL will change its reference from the serial data stream to the reference clock. When the peak input voltage is greater than LOSREF/10, the loss of signal condition will be deasserted and the PLL will recover the clock from the serial data inputs. In clock recovery mode, the receiver PLL also monitors the reference clock with respect to the VCO. If the VCO drifts away from the local reference clock by more than 1000 ppm the PLL will re-lock to the reference clock and the LOSOUT will be set to the active low condition. The LOSOUT will return to the High or inactive state and the PLL will again lock to the data if the serial data contains sufficient transition density (less than 100 to 200 bit times between rising edges), and the serial clock is within 250 ppm of the reference clock determined frequency.
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S3031B
In NRZ mode, a logic Low level on the LOSOPT input will cause the PLL to change its reference to the reference clock. This pin should be driven by a PECL compatible level signal detect signal from the fiber optic receiver. Serial Clock Output to Data Output Timing The serial data is clocked out on the falling edge of RSCLKOP. (See Figure 11.) This timing is valid in both NRZ and CMI modes. Serial to Parallel Converter The Serial to Parallel Converter consists of two 4-bit registers. The first is a serial-in, parallel-out shift register, which performs serial to parallel conversion clocked by the clock recovery block. The second is the output holding register. On the falling edge of the free running POCLK, the data in the serial-in, parallel-out register is transferred to the output holding register which drives POUT[3:0]. Input Jitter Tolerance Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 dB optical/electrical power penalty. OC-3 and E-4 input jitter tolerance requirements are shown in Figure 12. The S3031B PLL complies with the minimum jitter tolerance for clock recovery proposed for SONET/SDH equipment defined by the Bellcore TA-NWT-000253 standard when used as shown in Figure 12. The S3031B PLL also complies with the minimum jitter tolerance for clock recovery as defined in the ITU-T E4 specification when used as shown in Figure 19.
E4/STM-1/OC-3 ATM TRANSCEIVER
Reference Clock Input The reference clock input seen in Figure 9 provides backup reference clock signals to the clock recovery block when the clock recovery block detects a loss of signal condition. It contains a counter that divides the clock output from the clock recovery block down to the same frequency as the Reference Clock (REFCLK).
Figure 11. S3031B Clock to Data Timing
RSDATOP RSCLKOP/N
tPSER
Figure 12. Clock Recovery Jitter Tolerance Compliant to G.823 and G.825
Sinusoidal Input Jitter Amplitude (UI p-p) A2 A3 A4
f9 f9 f0 (Hz) (Hz) OC-3 10 30 STM-1 (Optical) 0.125 19.3 STM-1 (Electrical) 0.125 19.3 E4 TBD TBD f1 (Hz) 300 500 500 200
f0 f2 (kHz) 6.5 6.5 6.5 0.5
f1 f3 (kHz) 65 65 65 10
f2
f3
f4 A3 A4
A2 f4 (MHz) -- 1.3 1.3 3.5 15
1.5 0.15
391 1.5 0.15 391 1.5 0.15 15 1.5 0.075
Figure 10. Criteria for Determination of Transition Conditions. Compliant to G.775.
nominal value maximum cable loss
Note: 1. Only tested to 20 due to test equipment limitation.
3 dB 17
Tolerance range
"no transition condition" or "transition condition" may be declared
"transition condition" must be declared
35 Level below Nominal
"no transition condition" must be declared
The signal level 17 is (maximum cable loss +3) dB below nominal. The signal level 35 is greater than the maximum expected cross-talk level.
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E4/STM-1/OC-3 ATM TRANSCEIVER
Table 2. Transmitter Input Pin Assignment and Description
Pin Name TSTCLKEN Level TTL I/O I Pin # 26 Description
S3031B
Test Clock Enable. Active High. Enables the TESTCLK clock to be used in place of the VCO for testing. Allows a means of testing the functions of the chip without the use of the PLL. Diagnostic Line Code Violation. Set High to force a CMI line code violation. DLCV is only active in CMI mode. DLCV is sampled on the falling edge of TSCLKOP. DLCV does not affect XFRMSTATB or XFRMSTATB. CMI Select. Used to select a CMI or NRZ. A logic High selects CMI mode. A logic Low selects NRZ mode. Both the TSDATOP/N and the XFRMDRV outputs are controlled by CMISEL. Transmitter Reset. Active Low. Initializes the device to a known state. Serial data outputs are held to zero, and the Transformer Driver and Status outputs are forced Low. Loop Filter Capacitor Network. The loop filter capacitor network is connected to these pins. The capacitor value should be 1.0 F 10%, X7R dielectric. The resistors should be 100 for serial mode and 1000 for nibble mode operation. See Figure 18. Transformer Driver Enable. Used to enable the transformer driver output. A logic Low enables XFRMDRVA. A logic High turns off the transformer driver output. Transformer Driver Enable.Used to enable the transformer driver output. A logic Low enables XFRMDRVB. A logic High turns off the transformer driver output. Serial Data Enable. Used to enable the transmit serial data outputs. A logic Low enables TSDATOP/N. A logic High turns off the serial data outputs. Parallel Data Input. A 38.88 Mbyte/sec 4-bit wide Nibble aligned to the REFCLK reference clock. REFSEL and SERDSEL must both be at logic Low for transmitter operation with the nibble inputs. Transmit Serial Data In. The transmit clock is derived from transitions on these inputs when SERDSEL is High. No phase relationship to REFCLK is required. Either 19.44 MHz or 38.88 MHz reference operation may be selected. SERDSEL must be at logic High for transmitter operation with the serial data input.
DLCV
Singleended PECL TTL
I
86
CMISEL
I
27
TXRSTB
TTL
I
97
CAP1 CAP2
I
21 22
XFRMENA
TTL
I
92
XFRMENB
TTL
I
94
SERDATEN
TTL
I
8
PIN3 PIN2 PIN1 PIN0 TSDATIP TSDATIN
TTL
I
1 100 99 98 15 16
Diff. PECL
I
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S3031B
Table 3. Transmitter Output Pin Assignment and Description
Pin Name TSDATOP TSDATON Level Diff. PECL I/O O Pin # 12 13
E4/STM-1/OC-3 ATM TRANSCEIVER
Description Transmit Serial Data Out. In NRZ mode, this signal is the delayed version of the incoming data stream (TSDATIP/N) updated on the falling edge of Serial Clock Out (TSCLKOP). In CMI mode, this signal is the CMI-encoded version of TSDATIP/N. Transmit Serial Clock Out. This signal is a 155.52 MHz clock that is phase-aligned with Transmit Serial Data Out in NRZ mode. In CMI mode, TSCLKOP/N cannot be used. Transmit Reference Clock Out. Single-ended TTL reference clock output. Transformer Driver A. Used to drive the transformer of the electrical interface. For E4 operation this output should be connected per Figure 19 to provide the correct G.703 compatible output levels from the transformer when connected to the specified 75 cable. Transformer Driver B. Used to drive the monitor transformer of the electrical interface. This output should be connected per Figure 19 to provide the correct output levels from the transformer when connected to the specified 75 cable. Transformer Drive A Status. When High, the XFRMDRVA output is enabled, CMI mode is correctly selected, and the PLL is locked to switching data at the TSDATIP/N or PIN[3:0] input. Logic Low indicates deselection or code error. Transformer Drive B Status. When High, the XFRMDRVB output is enabled, CMI mode is correctly selected, and the PLL is locked to switching data at the TSDATIP/N or PIN[3:0] input. Logic Low indicates deselection or code error.
TSCLKOP TSCLKON TREFCLKOUT
Diff. PECL TTL
O
9 10 95
O
XFRMDRVA
Analog
O
89
XFRMDRVB
Analog
O
88
XFRMSTATA
TTL
O
93
XFRMSTATB
TTL
O
91
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E4/STM-1/OC-3 ATM TRANSCEIVER
Table 4. Receiver Input Pin Assignment and Description
Pin Name BUFINA BUFINB Level Analog I/O I Pin # 30 31 Description
S3031B
Buffer Inputs. Inputs to the equalizer network buffer circuit. This circuit provides a high impedance load to the transformer termination network in order to comply with the required return loss specifications. These pins should be connected as shown in Figure 19. These pins are electrically equivalent. Analog Data In. This is the serial data input from the equalizer circuit. It must be connected to the output of the equalizer circuit as shown in Figure 19. When the S3031B is used with a fiber optic receiver this input should be left open and the RSDATIP/N inputs should be used. Equalization Select Used to select RSDATIP/N or ANDATIN. A logic High selects ANDATIN. Receive Serial Data In. Clock is recovered from transitions on these inputs when selected by EQUALSEL. Receiver Reset. Active Low. Initializes the device to a known state, shuts off RSCLKOP/N, and forces the PLL to acquire to the reference clock. A reset of at least 16 ms should be applied at power-up and whenever it is necessary to reacquire to the reference clock. The S3031B will also reacquire to the reference clock if the serial data is held quiescent (constant ones or constant zeros), or LOSIN or LOSOPT are activated for at least 224 bit intervals. Input to 25dB gain block for internal equalizer function.
ANDATIN
Analog
I
46
EQUALSEL
TTL
I
51
RSDATIP RSDATIN RXRSTB
Diff. PECL TTL
I
66 65 75
I
GIN
Analog
I
36
LOSIN
Analog
I
48
Loss of Signal In. A single-ended input that indicates a loss of received signal. When the signal level at LOSIN drops below the voltage level set by LOSREF for greater than 100 to 200 bit intervals, the data on Serial Data Out (RSDATOP/N) will be forced to a constant low, and the PLL will change its reference from the serial data stream to the reference clock. This input is to be driven by the external bandpass filter and peak detect circuit as shown in Figure 19. This signal must be used to assure correct automatic reaquisition to serial data following an interruption and subsequent reconnection of the data path. This will assure that the PLL does not " wander" out of reaquisition range when no signal is applied. When LOSIN is inactive, data on the RSDATIP/N pins will be processed normally.
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S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Table 4. Receiver Input Pin Assignment and Description (Continued)
Pin Name LOSOPT Level PECL I/O I Pin # 52 Description Loss of Optical Signal. Active Low. This input has the same functionality as LOSIN, except that it is used in optical mode instead of electrical. It should be driven by the external optical receiver module to indicate a loss of received optical power. Loss of Signal Reference. Sets the comparator levels for LOSIN. (See Table 11.) Loop Filter Capacitor Network. The loop filter capacitor network is connected to these pins. The capacitor value should be 1.0F 10% tolerance, X7R dielectric. The resistors should be 51 . See Figure 18.
LOSREF
Analog
I
49
CAP3 CAP4
I
60 59
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E4/STM-1/OC-3 ATM TRANSCEIVER
Table 5. Receiver Output Pin Assignment and Description
Pin Name LOSOUT Level TTL I/ O O Pin # 74 Description
S3031B
Clock recovery indicator. Active Low. Set High when the internal clock recovery has locked onto the incoming datastream. LOSOUT is an asynchronous output. This output is deasserted when there is no incoming serial data input or when the received signal has dropped below the reference voltage set by LOSREF for more than 100 to 200 bit intervals. In this case the PLL locks to the reference clock. In clock recovery mode, the receiver PLL also monitors the reference clock with respect to the VCO. If the VCO drifts away from the local reference clock by more than 1000 ppm the PLL will re-lock to the reference clock and the LOSOUT will be set to the active Low condition. The LOSOUT will return to the High or inactive state and the PLL will again lock to the data if the serial data contains sufficient transition density (less than 100 to 200 bit times between rising edges), and the serial clock is within 250 ppm of the reference clock determined frequency. Receive Serial Data Out. This signal is the NRZ data output. It can be either a delayed version of the NRZ data input (NRZ mode) or the decoded CMI data (CMI mode). RSDATOP/N is updated on the falling edge of RSCLKOP as shown in Figure 11. Receive Serial Clock Out. This signal is phase-aligned with Serial Data Out (RSDATOP). (See Figure 11 and Table 7 for timing.) Line Code Violation. Set High to indicate that the current bit contains a CMI line code violation in CMI mode. LCV is updated on the falling edge of RSCLKOP/N. LCV output is undefined when running in NRZ mode. Buffer Output to the equalizer network buffer circuit. This circuit provides a low impedance driver to the equalizer circuit. This pin should be connected as shown in Figure 19 to drive the equalizer network. Parallel 4-bit wide output data bus, aligned to the parallel output clock (POCLK). POUT3 is the first bit transmitted, POUT0 is the fourth bit transmitted. POUT[3:0] is updated on the falling edge of POCLK. Parallel Output Clock. A 38.88 MHz nominally 50% duty cycle, nibble rate output clock that is aligned to the POUT[3:0] nibble serial output data. Output of 25dB gain block for the internal equalizer function. To be AC coupled to ANDATIN. See Figure 19.
RSDATOP RSDATON
Diff. PECL
O
69 68
RSCLKOP RSCLKON LCV
Diff. PECL SingleEnded PECL Analog
O
72 71 73
O
BUFOUT
O
33
POUT3 POUT2 POUT1 POUT0 POCLK
TTL
O
79 80 81 82 78
TTL
O
GOUT
Analog
O
44
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S3031B
Table 6. Common Pin Assignment and Description
Pin Name REFCLK Level TTL I/O I Pin # 6 Description
E4/STM-1/OC-3 ATM TRANSCEIVER
Reference Clock. Input used as the reference for the receiver VCO in the absence of received serial data. Used as the reference for the transmitter VCO in the serial input mode and in the absence of transmitter serial input data. In parallel transmit interface mode REFCLK is used as the reference for the internal bit clock frequency synthesizer and as the parallel load clock for the PIN[3:0] data. Reference Select. Used to select the reference clock frequency. A logic Low selects 38.88 or 34.816 MHz reference, and logic High selects 19.44 or 17.408 MHz. Serial Data Select. Active High. Used to select the Transmit Serial Data inputs (TSDATIP/N) and enable the Receiver Serial Data outputs (RSDATOP/N). In this mode the POUT[3:0] outputs are held Low. When SERDSEL is held at logic Low, the parallel inputs PIN[3:0] are selected and the the parallel outputs POUT[3:0] are enabled. Diagnosatic Loopback Enable. Active High. Selects diagnostic loopback. When DLEB is Low, the S3031B receiver section uses the RSDATIP/N or ANDATIN data inputs. When High, the S3031B receiver section uses the data from the transmitter section output. Line Loopback Enable. Active High. Selects Line Loopback. When LLEB is High the S3031B will route the data from the selected RSDATIP/N or ANDATIN inputs directly to the TSDATOP/N or XFRMDRVA/B outputs as selected. Test Clock. Used during device testing to bypass the VCO of the PLLs. Ground 0V
REFSEL
TTL
I
53
SERDSEL
TTL
I
96
DLEB
TTL
I
85
LLEB
TTL
I
84
TESTCLK
TTL
I
28
TXCRVEE TSVEE AVEE1 AVEE0 AVEE4 AVEE5 AVEE6 AVEE7 RXCRVEE AVEE2 AVEE3 RSVEE RXIOVEE TXIOVEE TXINVEE
GND
5 14 19 24 32 37, 38 39 50 54 57 62 64 76 90 2
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E4/STM-1/OC-3 ATM TRANSCEIVER
Table 6. Common Pin Assignment and Description (Continued)
Pin Name TXCRVCC TSVCC AVCC1 AVCC0 AVCC4 AVCC5 AVCC6 AVCC7 RXCRVCC AVCC2 AVCC3 RSVCC RXIOVCC TXIOVCC TXINVCC REFGND Level VCC I/O Pin # 4 11 18 25 29 34, 35 43 47 55 56 63 67 77 87 3 7 Description Power Supply (5V)
S3031B
GND
Ground (0V)
GND
GND
17 45 70 83 20 23 58 61 40 41 42
Gound (0V)
CGND
GND
Ground (0V)
NC
Not Connected.
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15
S3031B
Figure 13. 100-Pin PQFP/TEP Package
E4/STM-1/OC-3 ATM TRANSCEIVER
SIDE VIEW
TOP VIEW
Thermal Management
Device S3031
Power 1.92W
ja Still Air w/DW0045-28 19C/W
Max Still Air1 w/DW0045-28 85C
1. Max ambient temperature permitted in still air to maintain Tj < 130C.
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August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 14. Heat Sink Drawing DW0045-28
S3031B
August 19, 1999 / Revision D
17
S3031B
Figure 15. S3031B Pinout
E4/STM-1/OC-3 ATM TRANSCEIVER
PIN3 TXINVEE TXINVCC TXCRVCC TXCRVEE REFCLK REFGND SERDATEN TSCLKOP TSCLKON TSVCC TSDATOP TSDATON TSVEE TSDATIP TSDATIN GND AVCC1 AVEE1 CGND CAP1 CAP2 CGND AVEE0 AVCC0 TSTCLKEN CMISEL TESTCLK AVCC4 BUFINA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PIN2 PIN1 PIN0 TXRSTB SERDSEL TREFCLKOUT XFRMENB XFRMSTATA XFRMENA XFRMSTATB TXIOVEE XFRMDRVA XFRMDRVB TXIOVCC DLCV DLEB LLEB GND POUT0 POUT1
S3031B 100 PQFP/TEP TOP VIEW
18
BUFINB AVEE4 BUFOUT AVCC5 AVCC5 GIN AVEE5 AVEE5 AVEE6 NC NC NC AVCC6 GOUT GND ANDATIN AVCC7 LOSIN LOSREF AVEE7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
POUT2 POUT3 POCLK RXIOVCC RXIOVEE RXRSTB LOSOUT LCV RSCLKOP RSCLKON GND RSDATOP RSDATON RSVCC RSDATIP RSDATIN RSVEE AVCC3 AVEE3 CGND CAP3 CAP4 CGND AVEE2 AVCC2 RXCRVCC RXCRVEE REFSEL LOSOPT EQUALSEL
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E4/STM-1/OC-3 ATM TRANSCEIVER
Table 7. S3031B Clock Recovery Mode Performance Specifications
Parameter Nominal VCO Center Frequency OC-3/STS-3 Acquisition Lock Time1 Reference Clock Input Duty Cycle Reference Clock Rise & Fall Times PECL Output Rise & Fall Times Reference Clock Frequency Tolerance tPSER RSCLKOP Falling to RSDATO Valid Prop Delay 30 Min Typ 622.08 +8, -12 64 70 5.0 850 -100 100 Max Units MHz % sec % of UI ns ps pp m Condition
S3031B
Given REFCLK = VCO / 32 With respect to fixed reference frequency. With device already powered up and valid REFCLK.
20% to 80% of amplitude. 20% to 80%, 50 load, 5 pF cap.
100
1000
ps
See Figure 11.
1. Specification based on design values. Not tested.
Table 8. S3031B Clock Synthesis Mode Performance Specifications
Parameter PECL Data Output Jitter (RSDATOP/N) OC-3/STS-3 Min Typ Max Units Condition In CSU mode, Given 64 ps (rms) * 56 ps rms jitter on REFCLK in 12kHz to 1MHz band
E4-STS-3 CMI Reference Clock Frequency Tolerance Clock Synthesis
32
* 28 ps rms jitter on REFCLK in 12kHz to 1MHz band ppm Required to meet SONET output jitter generation specification.
-20
+20
Table 9. Electrical Characteristics for Transformer Driver1
(VCC = +5V, TA = +25C, input AC coupled unless otherwise noted.)
Parameter Operating Frequency VSWR
2
Min
Typ 155.52 1.3:1
Max
Units MHz
Condition 270 11 3pF load. 75 AC Coupled Termination.
1.5:1
1. For output waveform characteristics, see Figures 7 and 8. The S3031B is compliant with these masks on an individual waveform basis. The total cycle-to-cycle wideband jitter is less than 350 ps peak-to-peak. Total transmitted jitter per ITU G.825 is less than 0.075 UI peak-to-peak. 2. Up to 250 MHz.
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S3031B
Table 10. Electrical Characteristics for ANDATIN Input
(VCC = +5V, TA = +25C, input AC coupled unless otherwise noted.)
E4/STM-1/OC-3 ATM TRANSCEIVER
Parameter Peak-to-Peak Input Voltage Range Common-Mode Rejection Ratio Power-Supply Rejection Ratio Input Sensitivity DC Offset at Input 2
1. Up to 300 kHz. 2. Signal is undefined if left floating.
Symbol Viptp CMRR1 PSRR1 SIN
Min
Typ
Max 1.3
Units V dB dB mV
Conditions
40 40 110 Vcc -1V
TA = Min to Max
V
Table 11. Electrical Characteristics for LOSIN Input
(VCC = +5V, TA = +25C, input AC coupled unless otherwise noted.)
Parameter Peak-to-Peak Input Voltage Range Common-Mode Rejection Ratio Power-Supply Rejection Ratio Signal Level for LOS Detected3 Signal Level for LOS Cleared3 Hysterisis between "Trans. Cond." and "No Trans. Cond."2
Symbol Viptp CMRR1 PSRR1
Min
Typ
Max 1.1
Units V dB
Conditions
40 35 LOSLOSLOSREF/30 REF/20 REF/10 LOSLOSLOSREF/15 REF/10 REF/5 4 6
dB V/V V/V dB TA = Min to Max TA = Min to Max
1. Up to 300 kHz. 2. LOSREF >0.5 volts. 3. LOS detected and LOS cleared will maintain 2:1 ratio 5%.
Table 12. Typical Operating Conditions
Voltage Applied at LOSREF 1.4 Volts 0.7 Volts 0.3 Volts Compare Voltage #1 140 mV 0.6dB 70 mV 1dB 30 mV 1.6dB Compare Voltage #2 70 mV 1dB 35 mV 1.6dB 15 mV 3.5dB Hysterisis 6dB +1.6 -1.4dB 6dB +2.7 -2.0dB 6dB +6.0 -3.7dB
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E4/STM-1/OC-3 ATM TRANSCEIVER
Table 13. Electrical Characteristics for BUFIN, BUFOUT
(At VCC = +5VDC, RLOAD = 75 AC coupled and TA = 25C unless otherwise noted.)
S3031B
Parameter Output Characteristics (BUFOUT) Voltage Output: Output Resistance: Transfer Characteristics Gain (BUFIN to BUFOUT)1 VSWR2 Harmonic Distortion2 DC Input Bias DC Output Bias
1. Up to 300 MHz. 2. Up to 250 MHz.
Symbol
Min
Typ
Max
Units
Conditions
0.6 1 0.85 VSWR HD 35 30 25
0.8 3 0.93 1.3:1 40 35 30 Vcc -0.85 Vcc -2.5
8 1.1 1.5:1
V V/V With 75 AC Coupled termination dBc V V Input = 0.3V p-p Input = 0.6V p-p Input = 1.2V p-p Input externally AC Coupled Output externally AC Coupled
Table 14. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on VCC with respect to Ground Voltage on any TTL Input Pin Voltage on any PECL Input Pin TTL Output Sink Current TTL Output Source Current High Speed PECL Output Source Current Static Discharge Voltage
1. Human body model.
1
Min -65 -0.5 -0.5 Vcc -3
Typ
Max 150 +7.0 +5.5 Vcc 20 10 50
Units C V V V mA mA mA V
500
Table 15. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on any VCC with respect to Ground Voltage on any TTL Input Pin Voltage on any PECL Input Pin S3031B ICC Min -20 -10 4.75 0 VCC -2 336 5.0 Typ Max 85 +130 5.25 VCC VCC 365 Units C C V V V mA
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S3031B
Table 16. TTL Input/Output DC Characteristics
(TA = -20C to +85C, VCC = 5 V 5%)
E4/STM-1/OC-3 ATM TRANSCEIVER
Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Input High Current at max VCC Output Short Circuit Current Input Clamp Diode Voltage Output Low Voltage Output High Voltage
Symbol VIL1 VIH1 IIL IIH II IOS VIK VOL VOH
Min
Typ
Max 0.8
Units V V A
Conditions Guaranteed Input Low Voltage Guaranteed Input High Voltage VCC = MAX, VIN = 0.5 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 5.5 V VCC = MAX, VOUT = 0.5 V VCC = MIN, IIN = -18 mA VCC = MIN, IOL = 4 mA VCC = MIN, IOH = -1 mA
2.0 -400.0 50.0 1.0 -100.0 -1.2 0.5 2.7 -25.0
A mA mA V V V
1. These input levels provide zero noise immunity and should only be tested in a static, noise-free environment.
Table 17. PECL Input/Output DC Characteristics1,2
(TA = -20C to +85C, VCC = 5 V 5%)
Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Differential Voltage Input High Current Input Low Current Output Low Voltage Output High Voltage Output Differential Voltage
Symbol VIL VIH VIL VIH VID IIH IIL VOL VOH VOD
Min VCC -2.000 VCC -1.225 VCC -2.000 VCC -1.750 0.250 -0.500 -0.500 VCC -2.000 VCC -1.110 0.390
Typ
Max VCC -1.441 VCC -0.570 VCC -0.700 VCC -0.450
Units V V V V V A A V V V
Conditions Guaranteed Input Low Voltage for single-ended inputs Guaranteed Input High Voltage for single-ended inputs Guaranteed Input Low Voltage for differential inputs Guaranteed Input High Voltage for differential inputs Differential Input Voltage VID = 500 mV VID = 500 mV 50 termination to VCC -2V 50 termination to VCC -2V Differential Output Voltage
0.500
1.400 20.000 20.000 VCC -1.500 VCC -0.670 1.330
1. These conditions will be met with no airflow. 2. When not used, tie the positive differential PECL pin to VCC and the negative differential ECL pin to ground via a 3.9 k resistor.
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E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 16. Differential ECL Input Application
Zo=50 Fiber Optic Receiver 330 330 Zo=50 ECL driver to RSDATIP/N input 100
S3031B
RSDATIP RSDATIN
Figure 17. S3031B Differential ECL Output Application
TSDATOP TSDATON 330 330
Zo=50 100 Zo=50
Electrical to Optical
Figure 18. Loop Filter Capacitor Connections
R CAP1 1.0F R CAP2 CAP4 CAP3
51 1.0F 51
Note: R = 100 for serial mode, and R = 1000 for nibble mode.
August 19, 1999 / Revision D
23
S3031B
Figure 19. S3031B Transformer Input and Output Application
0.01 F 30 24 10 k CABLE OUT
E4/STM-1/OC-3 ATM TRANSCEIVER
0.01 F 30 24 10 k MONITOR OUT
220
XFRMDRVB
XFRMDRVA
220
AMCC S3031B
ANDATIN
BUFINA
BUFINB
BUFOUT
0.01F
C1 100 0.01F 0.01F 75pF 0.01F VCC 430 300
0 12pF RX INPUT 75 T 24pF
LOSREF
LOSIN
GIN
GOUT
0.4V
30
VCC 2.2 k
MMBD352
910 100pF 0.01F 0.01F 2.2 k 100pF
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August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 20. OC-3 Application
19.44 MHz
S3031B
TX_CLK_+/-
155.52 MHZ
TSCLKOP/N
SUNI IGT SYN155
RX_CLK_+/- RX_DATA_+/- 155.52 MHZ
S3031B
REFCLK RSCLKOP/N RSDATOP/N LOSOPT RSDATIP/N
O/E
TX_DATA_+/-
E/O
Figure 21. STM-1 CMI, E4 Application
19.44 MHz
REFCKIN TX_DATA_+/- TSDATIP/N XFRMDRVA Cable Output
XFRMDRVB
SUNI-LITE SUNI-PLUS SABRE
Monitor Output
S3031B
BUFIN
REFCLK RX_CLK_+/- RX_DATA_+/- RSCLKOP/N RSDATOP/N
Cable Input
BUFOUT ANDATIN EQUALSEL LOSIN LOSREF 0.01F
Equalizer
+5V
LOSIN Compensator
August 19, 1999 / Revision D
25
S3031B
Table 18. Suggested Interface Devices
Processor Interface PMC PM5345 PMC PM5346 PMC PM5347 IGT WAC-013-A TRANSWITCH SYN155 TI SABRE TDC 1500 Electrical Interface Motorola Mini-Circuits Mini-Circuits Optical Interface HP HFBR-520x CTS ODL-1408X Sumitomo SDM4123-XC AMP 269039-1 155 Mbps 155 Mbps 155 Mbps 155 Mbps MMBD352 MCL TXI-R5 MCL TO-75 Dual Diode SUNI SUNI-Lite SUNI-Plus
E4/STM-1/OC-3 ATM TRANSCEIVER
Saturn User Network Interface Saturn User Network Interface Saturn User Network Interface SONET LAN ATM Processor 155 Mbps Synchronizer 155 Mbps Processor
Wideband RF Transformer (Surface Mount) Wideband RF Transformer (Through-Hole) Fiber Optic Transceiver Fiber Optic Transceiver Fiber Optic Transceiver Fiber Optic Transceiver
Ordering Information
GRADE
S - industrial
RECEIVER
3031
PACKAGE
B - 100 PQFP/TEP w/DW0045-28 heatsink unattached
OPTION
H0 - No Heatsink
X
XXXX
IS
X
O 90 0
/
1
XX
H0 for no heatsink (identifier not marked on part)
Grade Part number
Package
RT
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation
26
E
D
CE
August 19, 1999 / Revision D

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